1(a)
F(w,x,y,z) = wʹxʹyʹzʹ + wʹxʹyzʹ + wxʹyʹzʹ + wʹxyʹzʹ + wʹxyz + wʹxyzʹ + wxʹyzʹ

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Minimal sum of products form: F(w,x,y,z) = x’z’ + w’z’ + w’xy

(b)

F (w,x,y,z) = xz’ + w’z’ + w’xy (using Only NAND Gates)

F
F

(c) (i)

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S (p,q,r) = p

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T (p,q,r) = pq’ + p’q = p XOR q

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U (p,q,r) = q’r + qr’ = p XOR r

(ii)

(d)(i)
Multiplexer
How it works: * A multiplexer is a combinational circuit which connects multiple input lines to a single output, allowing only a single selected input signal to be passed to the output line at a time. * An Input signal is selected to be passed to output based on selection code which is implemented as two select lines.

Typical Inputs and Outputs: * Consider a 4 -to -1 Multiplexer, typical inputs include four input lines labelled C0, C1, C2 and C3, along with two select lines labelled S0 and S1. * Output include single output line labelled F.

Labelled diagram of 4-to-1 Multiplexer:

(ii) Jk Flip Flop
How it works: * A JK flip-flop is a sequential circuit which has two inputs that are similar to that of an S-R flip-flop, however all possible combinations of input values are valid.

* If only the J input is asserted, the result is a set function, causing the output to be 1; if only the K input is asserted, the result is a reset function, causing the output to be 0.

* When both J and K are 1, the function performed is referred to as the toggle function: the output is complemented. Thus, if Q is 1 and 1 is applied to J and K, then Q becomes 0.

Typical Inputs and Outputs: * The JK flip flop has two main inputs signals ‘J’ and ‘K’ which are initially set to 0. * Output signals include Q and Q’, however the final output value of the circuit is the value of Q. * The flip-flop is constructed in such a way that the output of Q is also fed back as input through an AND gate along with K and a clock pulse.

* Similarly Q’ is fed back as input through an AND gate along with J and the same clock pulse.

Labelled diagram of JK Flip Flop:

(iii) 4-bit synchronous binary counter How it works: * Sequential circuit which goes through a predetermined sequence of states as the clock pulses. To produce an n-bit synchronous binary counter, n JK flip flops are needed.

* The flip flops are all connected to the same clock and are all simultaneously triggered at each clock pulse. With each clock pulse, the signals collectively released by the flip flops form a binary number.

* If we begin counting in binary: 0000, 0001, 0010, 0011, etc., we can see that as the numbers increase, the low-order bit is complemented each time. Whenever it changes state from 1 to 0, the bit to the left is then complemented.

* Each of the other bits change state from 0 to 1 when all bits to the right are equal to 1. Because of this concept of complementing states, binary counter is best implemented using a JK flip-flop.

* Instead of independent inputs to each flip-flop, there is a count enable line that runs to each flip-flop (with the help of an AND gate). The circuit counts only when the clock pulses and this count enable line is set to 1. A Synchronous 4-bit binary counter would be able to output binary numbers ranging from 0000 to 1111.

Typical Inputs and Outputs: * Inputs include input values from the count enable line, along with J and K which are all set to 1. * Output includes signal from flip flop labelled Q which is also fed as input into AND gate along with the count enable line. * The output signal from the AND gate “acts” as the count enable line for the remainder of flip flops. * The AND gate following nth flip flop has an output Carry which can be used to extend the range of the synchronous bit counter.

Labelled diagram of 4-bit Synchronous Counter:Flip flop 1
Flip flop 1

2(a)
Two approaches can be used to deal with multiple interrupts: 1. Disable interrupts while an interrupt is currently being processed. Interrupts remain pending until the processor enables interrupts. After interrupt handler routine completes, interrupts are then enabled before resuming program then the processor checks for additional interrupts i.e. interrupts are handled sequentially.

2. Define priorities for interrupts and to permit a higher priority interrupt which results in a lower-priority interrupt handler being interrupted itself.
(b)
Three typical functions that bus lines can be classified into are: 1. Data – these lines supply a path for the purpose of moving data among system modules. Collectively, these lines are referred to as the data bus. The width of the data bus is the number of lines that the bus consists of, each line can carry only 1 bit at a time and the number of lines determine how many bits can be transferred at a time. Therefore, overall system performance depends on the width of the bus.

2. Address – these lines indicate the source or destination of the data which is on the data bus. The maximum possible memory capacity of the system is determined the width of the address bus. Also, address lines are typically used to address I/O ports.

3. Control – these lines are utilized in controlling the access to and the utilisation of data and address lines. Control lines are the means for controlling data and address lines. Control and timing information are transmitted by control signals among system modules. Where control signals specify the operations to be performed and timing signals denote data validity and address information.

(c)
In single bus architecture, only one data item can be transferred over the bus in a clock cycle, the operation of the bus is as follows. If one module wishes to send data to another, it must do two things: 1. Obtain the use of the bus 2. Transfer data via the bus.
As all units are connected to this bus, the bus can be used for only one transfer at a time, only two units can actively use the bus at any given time. Bus control lines are used to arbitrate multiple requests for use of the bus.
To reduce the number of steps needed, most commercial processors provide multiple internal paths that enable several transfers to take place in parallel. Systems that contain multiple buses achieve more concurrency in operations by allowing two or more transfers to be carried out at the same time. This leads to better performance by the following ways: * In the multi-bus architecture there is a local bus that connects the processor to a cache memory which may support one or more local devices. * The cache memory controller connects the cache, not only to the local bus, but to a system bus to which are attached to all of the main memory modules. * Since the cache is in the same chip as the processor there is no need for an external bus or any other interconnected schemes. * It is possible to connect I/O controllers directly onto the system bus most efficiently by using one or more expansion buses.
(d)
A mezzanine bus is a high speed bus that is closely integrated with the rest of the system, requiring only a bridge between the processor’s bus and the high-speed bus. The mezzanine bus is a local bus that connects the processor to a cache controller, which is in turn connected to a system bus that supports main memory. The cache controller is integrated into a bridge, or buffering device, that connects to the high-speed bus. This bus supports connections to high-speed LANs, such as Fast Ethernet at 100 Mbps, video and graphics workstation controllers, as well as interface controllers to local peripheral buses. The advantage of this arrangement is that the high-speed bus brings high demand devices into closer integration with the processor and at the same time is independent of the processor.

(e) Five (5) elements of bus design are: 1. Type * Dedicated: this type of bus line is assigned permanently to either one function or to physical subset of computer components. * Multiplexed: this is a method in which the same lines are used for multiple purposes. 2. Method of Arbitration: this is the process for resolving disputes. * Centralized: in this scheme, a single hardware device called the arbiter or bus controller, is responsible for allocating time on the bus. The aforementioned device may be a separate module or part of the processor. * Distributed: in this scheme, each module contains access control logic and the modules act together to share the bus; there is no central controller. 3. Timing: describes the way in which events are regulated on the bus. * Synchronous: with this timing, the occurrence of events on the bus is resolved by the clock. * Asynchronous: with this timing, the instance of one event on a bus follows and is dependent on the occurrence of a prior event. 4. Bus Width: system performance and capacity are impacted the width of the data and address buses. * Data: a larger number of bits can be transferred simultaneously with a wider data bus. * Address: a greater range of locations can be referenced with a wider address bus. 5. Data Transfer Type: * Read * Write * Read-modify-write * Read-after-write * Block
(f)
Attribute | PCI (Peripheral Component Interconnect) | PCIe (Peripheral Component Interconnect Express) | Data Rate (I/O Devices) | Supports Lower capacity | Supports Higher capacity such as Gigabit Ethernet | Data Streams | Does not support | Supports time-dependent data streams | Interface | Parallel | Serial | Bus | Shared | Individual | Speed (16 slot) | 133MB per second | 16GB per second (Classified into lanes) | Slots | Same size (Standardized) | Varies based on the number of lanes the slot is intended for. |