COURSE OUTLINE

Computer Organization
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Objectives:
To introduce the following subjects: ▪ Organization of digital computers ▪ Different components ▪ Basic principles and operations.

Textbook: Stallings W., Computer Organization and Architecture: Designing for Performance, (9-th Edition) Prentice Hall, 2012.

References: ▪ Stallings W., Computer Organization and Architecture: Designing for Performance, (6-th Edition) Prentice Hall, 2003

▪ Stallings W., Computer Organization and Architecture: Designing for Performance, (5-th Edition) Prentice Hall, 2000.

▪ Mano M. M., Computer System Architec-ture (3-rd Edition), Prentice Hall, 1993.

▪ Stallings W., Computer Organization and Architecture: Principles of Structure and Function, 3-rd Edition) Macmillan Publishing Company, 1993.

▪ Wear L.L., Computer: An Introduction to Hardware and Software Design, McGraw Hill International Edition, 1991.

Subject Contents in Outline:

▪ Data Representation and Manipulation ▪ Digital Component ▪ Register Transfer and Microoperations ▪ Basic Computer Organization ▪ Overview of programming ▪ Central Processing Unit ▪ Input/Output Organization ▪ Memory Organization ▪ New development

Suggested Reading Assignments: Stallings William, Computer Organization and Architecture: Designing for Performance, (9th Edition) Prentice Hall, 2012.

Part II The Computer Systems Chapter 3 A Top-Level View of Computer Function and Interconnection (Pages 87- 115) (main) (Pages 116 – 129) (optional)

Part IV The Central Processing Unit Chapter 14 Processor Structure and Function (Pages 505 – 548) (optional)

Part VI The Control Unit Chapter 19 Control Unit Operation (Online resources, 9th Edition) (optional) or (Pages 579 – 602, 8th Edition) (optional)

▪ System Components ▪ Computer Function ▪ Micro-operations ▪ Register Organization ▪ Interconnection Structures ▪ Bus Interconnection
1. SYSTEM COMPONENTS

Central Processing Unit (CPU)

The most basic tasks handled by the CPU

Find and load the next instruction

Execute the instruction:

Fetch data from memory / registers Store data in memory / registers Perform calculations and comparisons Modify the instruction pointer (branching)

if A > B then Y:= A-B else Y:= A+B

The CPU is divided into three parts:

The Arithmetic Logic Unit (ALU) Carries out arithmetic, logical, and shifting operations

The Control Unit (CU) Fetches data and instructions and decodes addresses for the ALU. Registers

Registers

Registers are special work areas inside the CPU.

They are designed to be accessed at high speed.

Provide storage internal to the CPU.

The Intel instruction set requires the use of at least one register for nearly all instructions.

Major registers:

MAR, MBR, I/OAR, I/OBR

1. MAR - memory address register

specifies the address in memory for the next read or write.

2. MBR - memory buffer register

contains the data to be written into memory or receives the data from memory.

3. I/OAR - I/O address register

specifies a particular I/O device.

4. I/OBR - I/O buffer register

is used for the exchange of data between an I/O module and the CPU.

CPU Interconnection

Some mechanism that provides for communication among the control unit, ALU, and registers.

Memory

Consists of a set of locations defined by sequentially numbered addresses.

Each location contains a binary number that can be interpreted as either an instruction, or data.

[pic]

I/O

transfers data from external devices to CPU and memory, and vice versa

Contains internal buffers for temporarily holding this data until it can be sent

[pic]

Bus

The bus is a series of parallel wires that transmit data and control signals between the various parts of the computer.

[pic]

2. COMPUTER BASIC FUNCTION

The basic function performed by a computer is program execution

The program to be executed consists of a set of instructions stored in memory

The central processing unit (CPU) does the actual work by executing instructions specified in the program

Program execution consists of repeating the process of instruction fetch and instruction execution

The program counter (PC) - to keep track of which instruction is to be fetched next.

The instruction - a binary code that specifies what action the CPU is to take.

The fetched instruction is loaded into the instruction register (IR) in the CPU.

The CPU interprets the instruction and performs the required action.

The accumulator (AC) is used to temporarily store data.

Decoder

[pic]

Instruction Cycle

The processing required for a single instruction is called an instruction cycle:

Fetch cycle Execute cycle

Instruction Fetch:

is a common operation for each instruction consists of reading an instruction from a location in memory

Instruction Execution:

may involve several operations and depends on the nature of the instruction

At the beginning of each instruction cycle, the CPU fetches an instruction from memory.

[pic]

[pic]
In this example, 3 instruction cycles, each consisting of a fetch cycle and an execute cycle, are needed to perform A + B = C.
Micro-operations

Fetch

PC contains the address of the next instruction to be executed, it moves to MAR.

When the memory READ (control) is completed, the instruction is sitting in the MBR.

We then move the instruction into the IR.

Finally, we increment the PC by 1 so that it will correctly point to the next instruction when we get to the next fetch cycle.

1. MAR [pic] PC 2. READ 3. IR [pic] MBR 4. Incrementor [pic] PC 5. PC [pic] Incrementor

Execute

We determine what instruction is in the IR and issue the commands needed to carry it out.

Naturally, the exact sequence of signals will be different for every instruction.

LOAD instruction:

The address field of the IR is transferred to the MAR.

The contents of the location in memory the MAR provided are placed in the MBR by the control signal READ.

Finally, the MBR is moved to register R0.

MAR [pic] IRaddress MBR [pic] CON(address) R0 [pic] MBR

ADD instruction:

The address field of IR is moved to MAR.

The contents of the location in memory the MAR provided are placed in the MBR.

The MBR is moved to the adder

Send the contents of R0 to the adder

These two operands are added

The result is placed back in R0

MAR [pic] IRaddress MBR [pic] CON(address) Adder [pic] MBR Adder [pic] R0 ADD R0 [pic] Adder [pic]

1 Program Instructions Instruction Cycles Microprograms

3. Interconnection Structures

A computer consists of a set of components or modules of three basic types: ▪ processor ▪ memory ▪ I/O that communicate with each other.

In effect, a computer is a network of basic modules.

The collection of paths connecting the various modules is called the interconnection structure.

The design of this structure will depend on the exchanges that must be made between modules.

Computer Modules:

▪ Memory:

1. Typically, a memory module will consist of N words of equal length. 2. Each word is assigned a unique numerical address (0, 1, ...,N-1). 3. A word of data can be read from or written into the memory. 4. The nature of the operation is indicated by read and write control signals. 5. The location for the operation is specified by an address.

▪ I/O module:

1. From an internal (to the computer system) point of view, I/O is similar to memory. 2. Two operations: read and write. 3. Furthermore, an I/O module may control more than one external device (e.g, M devices). 4. Each external device has a port and each port has a unique address (e.g., 0,1,..., M-1). 5. There are external data paths for the input and output of data with an external device. 6. An I/O module may be able to send interrupt signals to the processor.

▪ Processor (CPU):

1. Reads in instructions and data, 2. Writes out data after processing, 3. Uses control signals to control the overall operation of the system, 4. It also receives interrupt signals.

The interconnection structure must support the following types of transfers:

▪ Memory to processor: The processor reads an instruction or a unit of data from memory.

▪ Processor to memory: The processor writes a unit of data to memory.

▪ I/O to processor: The processor reads data from an I/O device via an I/O module.

▪ Processor to I/O: The processor sends data to the I/O device

▪ I/O to or from memory: An I/O module is allowed to exchange data directly with memory, without going through the processor, using direct memory access (DMA).

4. Bus Interconnection

▪ A bus is a communication pathway connecting two or more devices.
▪ A key characteristic of a bus is that it is a shared transmission medium.
▪ Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus.
▪ If two devices transmit during the same time period, their signals will overlap and become garbled.
▪ Thus, only one device at a time can successfully transmit.
▪ Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.
▪ A bus that connects major computer components (processor, memory, I/O) is called a system bus.

Bus Structure

▪ A system bus consists, typically, of from 50 to 100 separate lines.
▪ Each line is assigned a particular meaning or function.
▪ On any bus, the lines can be classified into three functional groups : 1. Data lines 2. Address lines 3. Control lines.

• May have additional lines to supply electrical power
1. Data lines

▪ The data lines provide a path for moving data among system modules.
▪ These lines, collectively, are called the data bus.
▪ The data bus typically consists of 8, 16, 32, 64 or more separate lines, the number of lines being referred to as the width of the data bus.
▪ Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time.
▪ The width of the data bus is a key factor in determining overall system performance.
▪ For example, if the data bus is 8 bits wide and each instruction is 16 bits long, then the processor must access the memory module twice during each instruction fetch cycle.

2. Address lines

▪ The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory, it puts the address of the desired word on the address lines.
▪ The address lines are generally also used to address I/O ports.
▪ Typically, the higher-order bits are used to select a particular module on the bus, and the lower-order bits select a memory location or I/O port within the module.
▪ For example, on an 8-bit bus, address 01111111 and below might reference locations in a memory module (module 0) with 128 words of memory, and address 10000000 and above might refer to devices attached to an I/O module (module 1).

00000000 – 01111111--- memory address 10000000 – 11111111--- I/O address

3. Control lines

▪ The control lines are used to control the access to and the use of the data and address lines.
▪ Because the data and address lines are shared by all components, there must be a means of controlling their use.
▪ Control signals transmit both command and timing information among system modules.

Timing signals: indicate the validity of data, and address information. Command signals: specify operations to be performed.

Typical control lines include the following:

▪ Memory write: Causes data on the bus to be written into the addressed location. ▪ Memory read: Causes data from the addressed location to be placed on the bus. ▪ I/O write: Causes data on the bus to be output to the addressed I/O port. ▪ I/O read: Causes data from the addressed I/O port to be placed on the bus. ▪ Transfer ACK: Indicates that data have been accepted from or placed on the bus. ▪ Bus request: Indicates that a module needs to gain control of the bus. ▪ Bus grant: Indicates that a requesting module has been granted control of the bus. ▪ Interrupt request: Indicates that an interrupt is pending. ▪ Interrupt ACK: Acknowledges that the pending interrupt has been recognized. ▪ Clock: Used to synchronize operations. ▪ Reset: Initializes all modules.

The operation of the bus is as follows:

▪ If one module wishes to send data to another, it must do two things: (l) obtain the use of the bus, and (2) transfer data via the bus.

▪ If one module wishes to request data from another module, it must 1) obtain the use of the bus, and 2) transfer a request to the other module over the appropriate control and address lines. 3) It must then wait for that second module to send the data.

Bus Configurations

1. Traditional Bus Architecture

▪ There is a local bus that connects the processor to a cache memory and that may support one or more local devices.
▪ The cache memory controller connects the cache not only to this local bus, but to a system bus to which are attached all of the main memory modules.
▪ Some typical examples of I/O devices that might be attached to the expansion bus.
▪ Network connections include local area networks (LANs) such as a 10-Mbps Ethernet and connections to wide area networks such as a packet-switching network.
▪ SCSI (small computer system interface) is itself a type of bus used to support local disk drives and other peripherals.
▪ A serial port could be used to support a printer or scanner.
▪ An expansion bus interface buffers data transfers between the system bus and the I/O controllers on the expansion bus.

2. High-Performance Bus Architecture

▪ A high-speed bus that is closely integrated with the rest of the system, requiring only a bridge between the processor's bus and the high-speed bus.
▪ There is a local bus that connects the processor to a cache controller, which is in turn connected to a system bus that supports main memory.
▪ The cache controller is integrated into a bridge, or buffering device, that connects to the high-speed bus.
▪ The high-speed bus supports connections to high-speed LANs, such as Fast Ethernet at 100 Mbps, video and graphics workstation controllers, as well as interface controllers to local peripheral buses, including SCSI and FireWire.
▪ Lower-speed devices are still supported off an expansion bus, with an expansion bus interface between the expansion bus and the high-speed bus.

Clock and Timing

▪ Each of the individual operations within the CPU must be synchronized by a clock.

▪ The most basic unit of time for machine instructions is called the machine cycle.

▪ Each tick of the clock determines when the next machine cycle will occur.

▪ Machine instructions on Intel processors generally take between 3 and 20 clock cycles to execute, depending on whether they access memory or need to calculate a complex address.

▪ Timing refers to the way in which events are coordinated on the bus.

Timing: (1) Synchronous Timing (2) Asynchronous Timing

1. Synchronous Timing:

▪ The occurrence of events on the bus is determined by a clock. ▪ A clock transmits a regular sequence of alternating 1s and 0s of equal duration. ▪ A single 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot.

▪ All events start at the beginning of a clock cycle. ▪ Most events occupy a single clock cycle.

Example: (a synchronous read operation)

1. The CPU issues a read signal and places a memory address on the address bus. 2. CPU also issues a start signal to mark the presence of address and control information on the bus.

3. A memory module recognizes the address (second cycle) 4. After a delay of one cycle, the memory places the data and an acknowledgment signal on the bus.

2. Asynchronous Timing:

▪ The occurrence of one event on a bus follows and depends on the occurrence of a previous event.

Example: (a asynchronous read operation)

▪ The CPU places address and read signals on the bus.

▪ After pausing for these signals to stabilize, it issues an MSYN (master sync) signal, indicating the presence of valid address and control signals.

▪ The memory module responds with data and an SSYN (slave sync) signal, indicating the response.

▪ The master reads the data from the data lines,

▪ It deasserts the MSYN signal.

▪ This causes the memory module to drop the data and SSYN lines.

▪ Finally, once the SSYN line is dropped, the master removes the read signal and address information.

Synchronous timing is simpler to implement and test. However, it is less flexible than asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. With asynchronous timing, a mixture of slow and fast devices, using older and newer technology, can share a bus.

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CPU

Memory

Disk

Registers

Memory

Pointer

Y:=A-B

Y:=A+B

CPU

Registers

MBR

CU

ALU

MAR

I/O Module

Buffers

CPU

I/OAR

I/OBR

MAR

MBR

Registers

CPU Interconnection

Control Unit

Arithmetic & Logic Unit

Memory

Pointer

Y:=A-B

Y:=A+B

CPU

MBR

AC

MAR

Decoder

OP A B

IR

PC

+1

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R1

R2

R3

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MAR

MBR

IR

PC

R0 (AC)

ADDER

Memory

CPU

MBR

R0

MAR

BUS

LOAD Address

IR

1a

1d

1c

1b

3b

2a

2b

3a

5

Memory

CPU

MBR

R0

MAR

BUS

ADD Address

IR

1a

1d

1c

1b

2a

2b

ADDER

4

3

6

CU

ADD

Memory

CPU

BUS

IR

CU

Disk

2 A+B = C

3 LOAD A

4 Execution

5 Fetch

MAR ( PC
READ
IR ( MBR
PC + 1

MAR ( IR address
MBR ( CON(address)
AC ( MBR

6 ADD B

7 Execution

8 Fetch

MAR ( IR address
MBR ( CON(address)
ADDER ( MBR
ADDER ( AC
ADD
AC ( ADDER

MAR ( PC
READ
IR ( MBR
PC + 1

9 STOR C

10 Execution

11 Fetch

MAR ( IR address
MBR ( AC address ( MBR

MAR ( PC
READ
IR ( MBR
PC + 1

Write

Address

Data

Data

Memory

Read

0

N-1

1

N Words

I/O Module

Write

Address

Internal Data

External Data

External Data

Internal Data

Interrupt Signals

M Ports

Read

CPU

Instructions

Data

Data

Address

Control Signals

Interrupt Signals

CPU

Memory

Memory

I/O

I/O

Control Lines

Address Lines

Data Lines

Bus

Memory

0001 1100 1101 1110

IR: Instruction

0001 1100 1101 1110

8 bits

8 bits

8 bits

0001 1100
1101 1110

Control signals

Local Bus

Expansion
Bus Interface

Serial

Modem

SCSI

Network

Processor

Main
Memory

Local I/O
Controller

Cache

System Bus

Expansion Bus

Expansion
Bus Interface

Serial

Modem

Local Bus

Processor

Cache
/Bridge

System Bus

Main
Memory

SCSI

Graphic

FireWire

Video

LAN

High-Speed Bus

FAX

Expansion Bus

Clock

Start

Clock

Read

Address

Data

Acknowledge

Clock

Read

Address

Data

Acknowledge

Start

Read

Address

Read

Address

MSYN

Data

SSYN

MSYN

Read

Address

Data

SSYN

MSYN

Read

Address

Data

SSYN

Read

Address

Read

Address

MSYN

Read

Address

Data

SSYN