Abstract This report illustrates through the figures and results the procedures taken in this laboratory experiment to implement different Field Effect Transistor (FET) amplifier circuits. Firstly, is the procedure part which includes the design and results of whole task of the experiments and analyses the results of the task. the design and results part includes the tables, figures, equations and some comments about the results and it is divided into two tasks. The analyses the results part of the report investigate some errors of it. After that, the report is concluded through discussing the main achievements and the recommendations if found. The measured and simulated results are presented in this report along with a discussion of how the circuit parameters were determined.

1. Procedure
In this laboratory session, we dealt with another type of transistors known as the Field Effect Transistors (FET). Indeed, these transistors employ one type of charges, i.e. either electrons or holes depending on the channel polarity and hence the name unipolar devices arise. FETs are voltage controlled devices that have a very high input impedance and low noise level.

Task 1: Frequency response of FET amplifier

Task 2: Frequency response of Common-Drain FET amplifier:

In this task, we dealt with the frequency response of Common-Drain FET amplifier shown in Figure 1 below. A dc voltage of the value 15 V is applied to the drain while the Vgg is removed. In addition, a constant 200mVpp input voltage is applied. Then, the input frequency is changed from 10 Hz to 1MHz and a table that depicts the relation between the frequency and the output is produced.

It is a good practice to differentiate between the input and output terminals. Indeed, in this circuit, the Gate terminal of the transistor acts as the input while the output is taken at the Source, and the Drain is common between them.
In order to analyze the frequency response of the circuit, a range of input frequencies were set and the corresponding output voltages and gains for these frequencies were observed as shown in table 2. Figure 2 shows a screenshot of the input and the output signals when the frequency is 10 kHz using the oscilloscope. It is clear that the output voltage is almost equal to the input voltage; this means that the gain is 1.the phase shift on the other hand is almost zero; the output signal is in phase with the input signal. This amplifier circuit gives zero gain where the same input signal is found at the output. , as seen in the following relation. As the frequency of the input increases, we can see that the gain remains the same (≈ 0 dB), and the phase is almost zero (frequency change has no effect on the amplification).

Figure 3, shows the frequency response of the circuit. It is obvious that the gain is approximately constant for all frequencies (it looks fluctuating because the scale used is very small and those fluctuations could be due to human errors or to tolerance issues). The highest amplifier gain of this circuit is -0.34 dB. The -3 dB gain is not possible to get due to the limited range of data and due to the nature of this amplifier circuit. The information gathered is not enough to get the bandwidth of the circuit’s frequency response. On the other hand, the roll off per octave can only be obtained while the roll off per decade is not obtainable due to the limited information gathered and the nature of the amplifier circuit. The roll off per octave is: ƒ1= 200 kHz, ƒ2= 400 kHz
G1= -0.915149811 dB, G2= -0.526578774 dB roll off per octave = -0.526578774 - -0.915149811= 0.388571037 dB
Frequency Vin Vout G=VOUT/VIN G= 20 log G dt Phase Phase shift
Hz V V dB deg
10 0.198 0.18 0.909091 -0.827853703 1.00E-06 0.00 0
50 0.198 0.182 0.919192 -0.731876046 1.00E-06 0.00 0
100 0.204 0.184 0.901961 -0.896246888 1.00E-06 0.00 0
500 0.204 0.184 0.901961 -0.896246888 1.00E-06 0.00 0
1000 0.204 0.184 0.901961 -0.896246888 1.00E-06 0.00 0
5.00E+03 0.204 0.184 0.901961 -0.896246888 1.00E-06 0.00 0
1.00E+04 0.208 0.2 0.961538 -0.340666786 1.00E-06 0.00 0
2.50E+04 0.2 0.184 0.92 -0.724243453 1.00E-06 0.00 0
5.00E+04 0.2 0.184 0.92 -0.724243453 1.00E-06 0.00 0
7.50E+04 0.196 0.188 0.959184 -0.361964442 1.00E-06 0.00 0
1.00E+05 0.2 0.184 0.92 -0.724243453 1.00E-06 0.00 0
1.50E+05 0.2 0.184 0.92 -0.724243453 1.00E-06 0.00 0
2.00E+05 0.2 0.18 0.9 -0.915149811 1.00E-06 0.00 0
4.00E+05 0.204 0.192 0.941176 -0.526578774 1.00E-06 0.00 0
6.00E+05 0.2 0.188 0.94 -0.537442928 1.00E-06 0.00 0
8.00E+05 0.204 0.18 0.882353 -1.087153246 1.00E-06 0.00 0
1.00E+06 0.208 0.188 0.903846 -0.878109714 1.00E-06 0.00 0

2. Conclusions and Recommendations

To conclude, all the expected results match the implemented results successfully. Furthermore, the students are familiarized with the Field effect transistors and the concept of amplification. Moreover, the most important objective of this lab is achieved by understanding the behavior of the amplification process of the common-source and common-Drain amplifier transistor. The reason behind doing these tasks is to come out with the characteristics of the frequency response as well as getting all the measurements and values of the output voltage, the phase and calculated voltage gain. Finally, in order to display the behavior of the transistor, the frequency responses are sketched.