本科毕业设计(论文)

外文翻译（附外文原文）

学 院： 信息科学与工程学院 课题名称： 电子密码锁设计

专业(方向)： 电子信息科学与技术 班 级： 电信科技08-1班 学 生： 朱 日 科 指导教师： 陈 飞 日 期： 2012年5月10日

原 文

Hardware description language In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.[citation needed] HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics include explicit notation for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages used on electric computer-aided design (CAD). HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages, when they are more precisely classified as specification languages or modeling languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available. It is certainly possible to represent hardware semantics using traditional programming languages such as C++, although to function such programs must be augmented with extensive and unwieldy class libraries. Primarily, however, software programming languages do not include any capability for explicitly expressing time, and this is why they cannot function as hardware description languages. Before the recent introduction of SystemVerilog, C++ integration with a logic simulator was one of the few ways to use OOP in hardware verification. SystemVerilog is the first major HDL to offer object orientation and garbage collection. Using the proper subset of virtually any (hardware description or software programming) language, a program called a synthesizer (or synthesis tool) can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives to implement the specified behaviour.[citation needed]Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use clock edges as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language. History The first hardware description languages were ISP (Instruction Set Processor),[1] developed at Carnegie Mellon University, and KARL, developed at University of Kaiserslautern, both around 1977. ISP was, however, more like a software programming language used to describe relations between the inputs and the outputs of the design. Therefore, it could be used to simulate the design, but not to synthesize it. KARL included design calculus language features supporting VLSI chip floorplanning and structured hardware design, which was also the basis of KARL's interactive graphic sister language ABL, implemented in the early 1980s as the ABLED graphic VLSI design editor, by the telecommunication research center CSELT at Torino, Italy. In the mid 80's, a VLSI design framework was implemented around KARL and ABL by an international consortium funded by the commission of the European Union (chapter in [2]). In 1983 Data-I/O introduced ABEL. It was targeted for describing programmable logical devices and was basically used to design finite state machines. The first modern HDL, Verilog, was introduced by Gateway Design Automation in 1985. Cadence Design Systems later acquired the rights to Verilog-XL, the HDL-simulator that would become the de-facto standard (of Verilog simulators) for the next decade. In 1987, a request from the U.S. Department of Defense led to the development ofVHDL (VHSIC Hardware Description Language, where VHSIC is Very High Speed Integrated Circuit). VHDL was based on the Ada programming language. Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such as schematic files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands[citation needed]. The introduction of logic synthesis for HDLs pushed HDLs from the background into the foreground of digital design. Synthesis tools compiled HDL source files (written in a constrained format called RTL) into a manufacturable gate/transistor-level netlist description. Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance[citation needed]. A circuit design from a skilled engineer, using labor-intensive schematic-capture/hand-layout, would almost always outperform its logically-synthesized equivalent, but the productivity advantage held by synthesis soon displaced digital schematic capture to exactly those areas that were problematic for RTL synthesis: extremely high-speed, low-power, or asynchronous circuitry. In short, logic synthesis propelled HDL technology into a central role for digital design. Within a few years, both VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit simulation. Neither possesses language constructs to describe recursively-generated logic structures. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific Verilog/VHDL limitations, though none were ever intended to replace VHDL/Verilog. Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better testbench randomization, design hierarchy, and reuse. A future revision of VHDL is also in development, and is expected to match SystemVerilog's improvements. Design using HDL As a result of the efficiency gains realized using HDL, a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped in flowchart applications, or entered in a state-diagram editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style . The HDL is merely the 'capture language,' often beginning with a high-level algorithmic description such as a C++ mathematical model. Designers often use scripting languages (such as Perl) to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, and macro-based expansion of entity/architecture/signal declaration. The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as dangling ports or shorted outputs. This process aids in resolving errors before the code is synthesized. In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate netlist, this netlist is passed off to the back-end stage. Depending on the physical technology (FPGA, ASIC gate array, ASIC standard cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description. Finally, an integrated circuit is manufactured or programmed for use. Simulating and debugging HDL code Essential to HDL design is the ability to simulate HDL programs. Simulation allows an HDL description of a design (called a model) to pass design verification, an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design. To simulate an HDL model, an engineer writes a top-level simulation environment (called a testbench). At minimum, a testbench contains an instantiation of the model (called the device under test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. The testbench code is event driven: the engineer writes HDL statements to implement the (testbench-generated) reset-signal, to model interface transactions (such as a host–bus read/write), and to monitor the DUT's output. An HDL simulator — the program that executes the testbench — maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events. Modern HDL simulators have full-featured graphical user interfaces, complete with a suite of debug tools. These allow the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a defined PLI/VHPI interface. Linking is system-dependent (Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled and linked outside the HDL environment. Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's functional specification, the designer's interpretation of the specification, and the imprecision[citation needed] of the HDL language. The majority of the initial test/debug cycle is conducted in the HDL simulatorenvironment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware — programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes. Even those running on slow FPGAs offer much shorter simulation times than pure HDL simulation. Design Verification with HDLs Main article: Functional verification Historically, design verification was a laborious, repetitive loop of writing and running simulation test cases against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the EDA industry developed the Property Specification Language. In formal verification terms, a property is a factual statement about the expected or assumed behavior of another object. Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties cannot be proven because they occupy an unbounded solution space. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) more properties, over the narrowed solution space. The assertions do not model circuit activity, but capture and document the "designer's intent" in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion-based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset. HDL and programming languages A HDL is analogous to a software programming language, but with major differences. Many programming languages are inherently procedural (single-threaded), with limited syntactical and semantic support to handle concurrency. HDLs, on the other hand, resemble concurrent programming languages in their ability to model multiple parallel processes (such as flipflops, adders, etc.) that automatically execute independently of one another. Any change to the process's input automatically triggers an update in the simulator's process stack. Both programming languages and HDLs are processed by a compiler (usually called a synthesizer in the HDL case), but with different goals. For HDLs, 'compiler' refers to synthesis, a process of transforming the HDL code listing into a physically realizable gate netlist. The netlist output can take any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlist for post-synthesis place and route, or a generic industry-standard EDIF format (for subsequent conversion to a JEDEC-format file). On the other hand, a software compiler converts the source-code listing into a microprocessor-specific object-code, for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct. However, pure HDLs are unsuitable for general purpose software application development, just as general-purpose programming languages are undesirable for modeling hardware. Yet as electronic systems grow increasingly complex, and reconfigurable systems become increasingly mainstream, there is growing desire in the industry for a single language that can perform some tasks of both hardware design and software programming. SystemC is an example of such—embedded system hardware can be modeled as non-detailed architectural blocks (blackboxes with modeled signal inputs and output drivers). The target application is written in C/C++, and natively compiled for the host-development system (as opposed to targeting the embedded CPU, which requires host-simulation of the embedded CPU). The high level of abstraction of SystemC models is well suited to early architecture exploration, as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. However, the threading model used in SystemC and its reliance on shared memory mean that it does not handle parallel execution or lower level models well. In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level of the design. Companies such as Cadence, Synopsys and Agility Design Solutions are promoting SystemC as a way to combine high level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs. Approaches based on standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the Catapult C tools from Mentor Graphics, the Impulse C tools from Impulse Accelerated Technologies, and the free and open-source ROCCC 2.0 tools from Jacquard Computing Inc. Annapolis Micro Systems, Inc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry. Languages such as SystemVerilog, SystemVHDL, and Handel-C seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive versus making FPGAs more accessible to existing software engineers.

译文 硬件描述语言 在电子中，硬件描述语言或HDL是任何一类的语言，计算机语言，规范语言，或建模语言形式化描述和电子电路设计，最常用的数字逻辑。它可以用来描述电路的操作，其设计和组织，并测试，以验证其操作的模拟手段。 HDL的标准文本为基础的电子系统的时间和空间的结构和行为的表达。HDL的语法和语义的并发编程语言一样，包括并发明确表示符号。然而，在大多数软件编程语言相比，HDL还包括一个明确的时间概念，这是一个主要的硬件属性。语言，其特点是表示电路块的层次结构之间的连接是否正确归类为网表电动计算机辅助设计（使用的语言CAD）。 HDL是用来写可执行的硬件规格。旨在实现潜在语义的语言陈述的程序，与模拟时代的进步提供了一块硬件建模的能力之前，它是创建物理硬件设计师。这是这个可执行，使HDL是错觉的编程语言，当他们更精确地归类为规范语言或建模语言。模拟器能够支持离散事件（数字）和连续时间（模拟）建模存在，并针对每个HDL是可用的。 这当然是可以代表硬件的语义，使用传统的编程语言如C + +中，虽然这种方案必须广泛而笨重的类库增强运作。为主，然而，软件编程语言，不包括任何明确表示时间的能力，这就是为什么他们不能正常工作的硬件描述语言。最近推出的SystemVerilog之前，C + +的集成与逻辑模拟器使用的为数不多的途径之一OOP在硬件验证。SystemVerilog是第一个主要的HDL提供的面向对象和垃圾收集。 使用几乎任何语言（硬件描述或软件编程）的子集，一个程序称为合成（或合成工具）可以推断，从语言的语句硬件逻辑运算，产生相当于一个通用的硬件原语的网表执行指定的行为。合成一般忽略任何时间在文本构建的表达。例如，数字逻辑合成，一般使用时间电路的时钟边沿，忽略任何时间结构。有一个语言的可综合子集的能力本身并不使硬件描述语言。 第一硬件描述语言的ISP（指令集处理器），在卡内基-梅隆大学，卡尔，双方围绕1977年，在凯泽斯劳滕大学开发。ISP的是，然而，更像一个软件编程语言，用来描述设计的输入和输出之间的关系。因此，它可以用来模拟设计，但不能合成。卡尔迈耶包括设计演算的语言功能，支持超大规模集成电路芯片平面布局和结构的硬件设计，这是也根据卡尔的交互式图形妹妹语言ABL的，禁止图形超大规模集成电路设计编辑在20世纪80年代初实施，“电信研究中心CSELT在都灵，意大利。VLSI设计框架是在80年代中期，卡尔和ABL左右实施由欧盟委员会（章中资助的一个国际财团）。数据的I / O在1983年推出了亚伯。它是针对描述可编程逻辑器件，基本上被用来设计有限状态机。 在1985年第一届现代HDL（HDL），Verilog的，介绍了网关设计自动化。Cadence设计系统公司后来收购的Verilog-XL，HDL模拟器，将成为事实上的标准为下一个十年（Verilog仿真）的权利。1987年，从美国国防部的要求导致VHDL（超高速集成电路硬件描述语言，其中超高速集成电路是非常高速集成电路）的发展。VHDL语言Ada编程语言的基础上。最初，Verilog和VHDL，用于记录和模拟电路设计已经抓获，另一种形式（如原理图文件）中所述。HDL仿真，使工程师工作在更高的抽象水平比在原理图级仿真，从而增加从数百数千个晶体管的设计能力。 引进的HDL的合成逻辑推从背景到前景的数字化设计的HDL。合成工具编译HDL源文件（称为约束的格式编写的RTL）到制造的门/晶体管级网表描述。编写综合的RTL需要设计师的实践和纪律的文件;相比传统的原理图布局，合成的RTL网表几乎总是更大的面积和性能慢。从使用劳动力密集型schematic-capture/hand-layout，一个熟练的工程师，电路设计，几乎总是会超越其相当于逻辑合成，但合成举行的生产率优势很快取代数字的原理图捕获正是这些领域的问题RTL综合：超高速，低功耗，或异步电路。总之，逻辑综合推动HDL技术进入了数字化设计的核心作用。 在短短几年内，VHDL和Verilog成为电子行业中占主导地位的HDL，从使用逐渐消失，而老年人和能力较差的HDL。然而，VHDL和Verilog有着许多相同的局限性：HDL胆固醇都不是合适的模拟/ 混合信号电路仿真。既不具有语言结构来描述递归生成的逻辑结构。介绍了专门的HDL（如合流）有明确的目标，确定具体的Verilog / VHDL限制，虽然没有以往任何时候都打算更换的VHDL / Verilog。 多年来，已投入很多努力，在提高HDL。最新一轮的正式称为IEEE 1800-2005 SystemVerilog的Verilog的，引入了许多新的功能（类，随机变量，属性/断言）随机更好的测试平台，设计层次，再利用，以解决日益增加的需求。未来修订的VHDL也是在发展，并有望匹配SystemVerilog中的改进。

设计使用的HDL

为提高效率，使用HDL，大多数现代数字电路设计，围绕着它。大部分设计开始作为一组需求或一个高层次的建筑图。控制和决策结构往往原型在流程图的应用程序，或在状态图编辑器输入。编写HDL描述的过程是高度依赖于电路的性质和设计师的编码风格偏好。HDL仅仅是“捕捉语言”，往往一个高层次的，如一个C + +数学模型的算法描述开始。设计者通常使用的脚本语言（ 如Perl ）自动生成HDL语言重复的电路结构。特殊的文字编辑器提供了自动缩进功能，依赖语法着色，基于宏观扩张实体/建筑/信号声明。 HDL代码，然后经历了一个代码审查或审计。在准备进行合成，HDL描述的是受自动化跳棋阵列。跳棋报告从标准化代码准则的偏差，找出潜在的含糊不清的代码结构，才可以引起误解，并检查常见的逻辑编码的错误，如港口或输出短路晃来晃去，。这个过程有助于解决之前的代码合成的错误。 在HDL设计行业的说法，一般在合成阶段结束。一旦合成工具门网表映射到HDL描述，这个网表传递到后端阶段。根据物理技术（FPGA，ASIC 标准单元ASIC的 门阵列），HDL可能会或可能不会发挥了重要作用，在后端流程。在一般情况下，作为设计流程的走向实际变现的形式进行，设计数据库技术的具体信息，这是不能被储存在一个通用的HDL描述逐渐变得更加载货。最后，集成电路制造或使用编程。

仿真和调试的HDL代码

HDL设计的关键是模拟HDL方案的能力。仿真允许一个设计的HDL描述（称为模型），通过设计验证，验证设计的HDL描述（规格）的代码实现预期的功能，对一个重要的里程碑。它也允许建筑的探索。工程师可以写的底座设计的多种变化，然后比较它们的行为在仿真试验设计选择。因此，模拟是成功的HDL设计的关键。 以模拟HDL模型，工程师写一个顶层的仿真环境（称为测试平台）。至少，一个测试包含一个实例的模型（称为下测试或待测设备），引脚/信号的声明，该模型的I / O和时钟波形。测试平台的代码是由事件驱动的工程师写的HDL语句来实现的（测试平台生成）复位信号，模拟接口的交易（如主机总线读/写），并监测DUT的输出。-计划，执行测试平台- HDL模拟器，维护模拟器的时钟，这是在测试平台模拟的所有事件的主参考。事件发生在测试平台的HDL（如复位切换到测试平台编码）决定的瞬间，或反应（模型）刺激和触发事件。现代的HDL模拟器有功能齐全的图形用户界面，调试工具套件。这允许用户停止和重新启动模拟在任何时间，插入模拟器断点（HDL代码无关），监视或修改HDL模型的层次结构中的任何元素。现代的模拟器还可以向用户编译的库连接的HDL环境，通过定义PLI / VHPI接口。链接是依赖系统（WIN32 / 的Linux / SPARC），HDL仿真器和用户库编译和链接以外的HDL环境。 设计验证是经常的设计过程中最耗时的部分，由于设备的功能规范，规范设计师的解释，不精确HDL语言之间的脱节。大多数的初步测试/调试周期的HDL 仿真环境中进行，设计的早期阶段是受频繁和主要电路的变化。HDL描述也可以被原型和测试硬件- 可编程逻辑器件通常用于这一目的。硬件原型是较为昂贵，但比HDL仿真的设计提供了一个现实世界的看法。原型是最好的检查方法对其他硬件设备的接口和硬件原型。即使是那些运行缓慢的FPGA提供比纯HDL仿真模拟时间要短得多。

设计验证与HDL

从历史上看，设计验证是一个艰苦的反复循环，编写和运行仿真测试用例对被测设计。作为芯片设计变得更大和更复杂，设计验证任务已发展到的地步，现在占主导地位的一个设计团队的时间表。寻找方法提高了设计生产力，EDA产业开发物业的规范语言。 在正式的核查条款，物业是另一个对象的预期或假设的行为有关的事实陈述。理想的情况下，对于一个给定的HDL描述，属性或属性可以被证明是真的还是假的，使用正规的数学方法。在实践中，许多物业不能被证明，因为他们占据了无限的解空间。但是，如果提供了一套经营假设或约束，属性检查器可以证明（或否定）更多的属性，在缩小解空间。 断言没有模型电路的活动，但捕捉并记录在HDL代码“设计师的意图”。在模拟环境中，模拟器评估所有指定的断言，报告的地点和任何违规行为的严重性。在合成环境中，综合工具通常经营的政策，制止任何违反后的合成。基于断言的验证仍处于起步阶段，但有望成为HDL设计工具的一个组成部分。

HDL和编程语言

HDL是类似的软件编程语言，但有重大分歧。固有的程序（单线程），有限的语法和语义处理并发的支持，许多编程语言。另一方面，HDL，类似的并发编程语言在自己的能力模型的多个并行进程（如触发器，加法器等）自动执行相互独立的。任何变化过程的输入，自动触发更新模拟器的进程堆栈。处理这两种编程语言和HDL编译器（通常称为合成HDL的情况下），但与不同的目标。对于HDL，“编译器”是指合成，物理变现门网表转化为HDL代码上市的过程。网表输出，可以采取多种形式：“模拟”网表与门延迟的信息，“切换”合成后的网表地点和路线，或一个通用的行业标准的EDIF随后转换为格式（JEDEC -格式的文件）。 另一方面，软件编译器的源代码清单转换成微处理器的特定对象的代码，目标微处理器的执行。由于HDL和编程语言的相互借鉴的概念和功能，它们之间的边界正变得那么不同。但是，纯粹的HDL是不适合通用 应用软件开发的通用编程语言，就像是不可取的硬件建模。然而，作为电子系统变得越来越复杂，可重构系统变得越来越主流，在同行业中有越来越多的欲望为一个单一的语言，硬件设计和软件编程，可以执行一些任务。SystemC是等嵌入式系统的硬件的一个例子可以作为非详细的建筑块（黑盒模拟的信号输入和输出驱动器）为蓝本。目标应用程序编写的C / C + +和本地编译为主机开发系统（而不是针对嵌入式CPU，这就要求嵌入式CPU的主机仿真）。SystemC模型的抽象的高层次以及适合于早期建筑勘探，建筑修改，可以很容易地评估小信号一级的执行问题的关注。然而，线程模型用于SystemC和共享内存的依赖，意味着它不能处理并行执行或更低级别车型。 在试图减少HDL，已相当于设计汇编语言的复杂性，有动作，以提高设计的抽象层次。如公司的Cadence，Synopsys和敏捷性设计解决方案正在推动的SystemC作为一种并发模型结合的高层次的语言，以便更快的设计周期，为FPGA，可能比使用传统的HDL。方法基础上的标准ç或ç+ +库或其他扩展允许并行编程被发现的投石器ç从工具Mentor Graphics公司的冲击ç脉冲加速技术工具，免费开源ROCCC 2.0从工具提花计算安纳波利斯微系统公司的公司。CoreFire设计套件和NI公司的LabVIEW FPGA提供高层次的设计进入一个图形化数据流的方法。如语言SystemVerilog的，SystemVHDL和韩德尔- C，寻求实现同样的目标，但目的是使现有的硬件工程师与FPGA越来越多地接触到现有的软件工程的生产。