Timers and Counters
Exercise 2.2 1. Define the following timer bits: timer enable, timer timing, and timer done.
ANSWER: Timer enable bit: The enable bit is true when the rung input logic is true, and the enable bit is false when the rung input logic is false. When the EN bit is true the timer accumulator is incrementing at the rate set by the timer time base.
Timer timing bit: indicates when timing action is occurring and can be used to control timed events in automation applications.
Timer done bit: the end of the timing process by changing states from false to true or from true to false depending on the type of timer instruction used. 2. Compare and contrast the true and false states of the timer timing bit for the on-delay timer, the off-delay timer, and the retentive timer.
ANSWER: In the true states for all three have the accumulator value is less than the preset value, but for off-delay timer the timer rung is false unlike the retentive timer and on-delay that the timer rung is true.
In the false states for all three have the accumulator is equal to or greater than the preset value. Like the true state retentive timer and on-delay timer both have the same condition and that are false if the timer rung is false, but the on-delay timer has other condition that are false if the timer done bit is true. The off-delay has a condition that are false if the timer done is false. 3. What is the difference between a retentive timer and a non-retentive timer?
ANSWER: A non-retentive timer's accumulator will reset when the enabling input is reset but the retentive will not reset when the enabling bit is reset, only when the timer's reset input is enabled, or when the timer is done. 4. Explain why the counters in PLC applications are typically retentive.
ANSWER: The counter instructions of a PLC are normally retentive. The counter will either increment or decrement whenever the count input transfers from an off state to an on state 5. What is the difference between the overflow bit and the underflow bit?
ANSWER: The overflow bit is true whenever the counter counts past its maximum value. The underflow bit will go true when the counter counts below the preset. 6. In an application that requires an up/down counter, why must the counters be located at the same address?
ANSWER: So that the up, down, and reset actions can be performed on the same counter if desired. 7. Identify the type of counter you would choose for each of the following applications. a. Accumulate the total number of components made during the night shift.
ANSWER: Up counter b. Keep track of the number of parts remaining in a bin as parts are extracted. Assume that a full bin contains 24 parts.
ANSWER: down counter c. Keep track of the current number of parts at the first stage of a process as they enter and exit.
ANSWER: Up/down counter 8. Compare and contrast the true and false states of the overflow and underflow bits for the up counter and the down counter.
ANSWER: True states: The overflow bit is true whenever the counter Counts past its maximum value. The underflow bit will go true when the counter counts below the preset. False states: False states the opposite